3.1.7
Axis Configuration Registers (DEVCFG_X, DEVCFG_Y)
The Axis configuration registers are read/write registers which contain axis specific configuration information. These registers
can be written during initialization, but are locked once the ENDINIT bit is set. These registers are included in the writable register
CRC check. Refer to Section 3.2.2 for details.
Table 10. Axis Configuration Registers
Location
Bit
Address
$0C
$0D
Register
DEVCFG_X
DEVCFG_Y
7
ST_X
ST_Y
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
LPF_X[3]
LPF_Y[3]
2
LPF_X[2]
LPF_Y[2]
1
LPF_X[1]
LPF_Y[1]
0
LPF_X[0]
LPF_Y[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.7.1 Self Test Control (ST_X, ST_Y)
The ST_X and ST_Y bits enable and disable the self test circuitry for their respective axes. Self test circuitry is enabled if a
logic ‘1’ is written to ST_X, or ST_Y and the ENDINIT bit has not been set. Enabling the self test circuitry results in a positive
acceleration value on the enabled axis. Self test deflection values are specified in Section 2.4 . ST_X and ST_Y are always
cleared following internal reset.
When the self test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status
bits in the Acceleration Data Request Response will indicate “Self Test Active”. Reference Section 3.8.4 and Section 4.2 for de-
tails. When the self test circuitry is disabled by clearing the ST_X or ST_Y bit, the offset monitor remains disabled until the time
t ST_OMB specified in Section 2.6 expires. However, the status bits in the Acceleration Data Request Response will immediately
indicate that self test is deactivated.
When ENDINIT is set, self test is disabled. This can only be changed by a reset. A Register Write will not modify the ST_X
and ST_Y bits and the response to a Register Read or Write will include the last successful written values for these bits.
3.1.7.2 Reserved Bits (Reserved)
Bits 6 through 4 of the DEVCFG_X and DEVCFG_Y registers are reserved. A write to the reserved bits must always be logic
‘0’ for normal device operation and performance.
3.1.7.3 Low-Pass Filter Selection Bits (LPF_X[3:0], LPF_Y[3:0])
The Low Pass Filter selection bits independently select a low-pass filter for each axis as shown in Table 11 . Refer to
Section 3.8.3 for details regarding filter configurations.
Table 11. Low Pass Filter Selection Bits
LPF_X[3] /
LPF_Y[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LPF_X[2] /
LPF_Y[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LPF_X[1] /
LPF_Y[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LPF_X[0] /
LPF_Y[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Low Pass Filter Selected
100 Hz, 4-pole
300 Hz, 4-pole
400 Hz, 4-pole
800 Hz, 4-pole
1000 Hz, 4-pole
400 Hz, 3-pole
Reserved
Reserved
50 Hz, 4-pole
150 Hz, 4-pole
200 Hz, 4-pole
400 Hz, 4-pole
500 Hz, 4-pole
200 Hz, 3-pole
Reserved
Reserved
Nominal Sample Rate ( μ s)
8
8
8
8
8
8
Reserved
Reserved
16
16
16
16
16
16
Reserved
Reserved
Note: Filter characteristics do not include g-cell frequency response.
MMA65xx
Sensor
Freescale Semiconductor, Inc.
17
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